This article presents a family of NPC inverters consisting of single-phase, three-phase, and cascaded inverters. The proposed inverters have no short-circuit and dead-time issues, therefore no high voltage and current spikes are caused. Also, the dead-time in the switching signals can be minimized.
The voltage stress of the semiconductor devices in the proposed inverter is half of the source voltage, whereas in the conventional DB-NPC inverter the voltage stress of the two external diodes is the source voltage. In addition to the aforementioned benefits, the proposed cascaded inverter reduces the total number of inductors.
However, the voltage stress of the two external diodes in the DB-NPC inverter is higher. On the other hand, the SI-NPC inverter has a problem of generating huge voltage spikes in the dead-time, which can destroy the semiconductor devices. In addition, the SI-NPC inverter cannot provide reactive power.
Abstract: The traditional neutral point clamped (NPC) inverter has short-circuit problem. The risk of short-circuit can be decreased by using dead-time in the switching signals. However, the dead-time decreases the achievable output voltage and causes distortion in the waveforms.
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Additionally, the five-level NPC inverter offers benefits like lower switching losses, balanced voltage stress across components, and modularity for scalability in high-power …
The proposed topology is derived from the conventional ANPC by adding one additional capacitor to boost the voltage and increase the number of output voltage levels. Similar to other …
I. INTRODUCTION The three-level neutral point clamped (NPC) inverter is suitable for medium and high voltage drive applications because the voltage stress on its switching …
Integrating a quasi-Z-source (qZS) network with a 3L-NPC topology enhances the inverter''s performance by reducing voltage stress on components, minimizing harmonic …
Particularly, it discusses voltage stress on power switches in Active NPC converters, presenting experimental results from high-power …
The voltage stress of the semiconductor de-vices in the proposed inverter is half of the source voltage, whereas in the conventional DB-NPC inverter the voltage stress of the two …
The advantages of three-level neutral-point-clamped (NPC) H-bridge inverters, such as simple topological structure, low device …
The main disadvantage of NPCI [9] is the unbalance in capacitor voltage and common mode voltage. Uneven commutation amongst switching devices, non-ideal dc link …
The results confirm that the proposed model predictive controlled ANPC inverter equally distributes the voltage across all the semiconductor power switches and provides …
Particularly, it discusses voltage stress on power switches in Active NPC converters, presenting experimental results from high-power 3ph UPS implementation.
These topologies are also the subject of intensive research and, in several publications [4] [5] [6] [7] [8], certain research problems …
This voltage stress problem is solved by using the active neutral-point-clamped (ANPC) which offers additional zero switching states by employing two active switches in …
NPC inverter topology is introduced to improve the DC-link voltage utilization ratio and alleviate the voltage stress on power switches, for which its output voltage has multiple levels [32].
Abstract Neutral Point Clamped Three-Level Inverter (NPC TLI) is widely used in medium and high voltage speed regulation systems, grid-connected power generation and …
The voltage stress of the semiconductor devices in the proposed inverter is half of the source voltage, whereas in the conventional DB-NPC inverter the voltage stress of the two …
It was inferred that as the number of levels in an Inverter increase, the harmonic distortion as well as voltage stress over each switch reduces considerably. The switching …
Fig.1 represent a block diagram for a MLI. Neutral point converter which was proposed by Nabae, Takahashi and Akagi in 1981. Some features of the NPC inverter are …
In this paper, space vector pulse width modulation technique is proposed to reduce the common-mode voltage (CMV) of a five-phase three-level neutral point clamped inverter. …
This paper has proposed a hybrid seven-level inverter topology with a boosting capability three times that of conventional seven-level inverter topologies. It contains ten …
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